1) Field of the Invention
The present invention relates to a technology for forming a tree structure type circuit that has a tree distribution structure. More particularly, this invention relates to a method of forming a tree structure type circuit such as a clock circuit designed by a method of forming a clock tree, and a computer product.
2) Description of the Related Art
Generally, in designing a layout of large-scale integration (LSI), a clock circuit is often constituted by a tree structure type circuit using the method of forming a clock tree so as to prevent a clock skew. Conventionally, such a tree structure type circuit is automatically formed by a layout tool or the like.
As a method of forming a tree structure type clock circuit, for example, the following two methods have been known. A first method is realized by forming a tree circuit before layout. A tree structure shown in FIG. 1 is formed in accordance with a flow chart shown in FIG. 2 (step S101). Timing driven placement of buffers and circuit elements that does not consider a clock skew is conducted to the tree structure distribution circuit as shown in FIG. 3 (step S102), and routing is conducted to the buffers, circuit elements, and the like thus placed (step S103).
A second method is realized by forming a tree circuit after initial layout. That is, timing driven placement is conducted to a circuit without considering a tree structure as shown in FIG. 4 in accordance with a flow chart shown in FIG. 5 (step S131). It is assumed that this initial placement has either timing with which there is no clock skew or timing with which a fixed margin is provided. As shown in FIG. 6, a tree structure is formed, followed by placement and routing (step S132). At this time, the tree structure is optimized to the layout of a distribution target circuit, so that consumption of routing resources is minimized. Thereafter, based on the tree structure, timing driven placement is improved in view of the actual skew of a clock (step S133), and routing is performed (step S134).
According to the first conventional method, however, in the tree structure as shown in FIG. 1, no consideration is given to coordinates “a”, “b”, “c”, “x”, “y”, and “z” of elements 11, 12, 13, 14, 15, and 16 that are located at the terminal ends of the distribution circuit, respectively. The tree structure is not, therefore, an optimum tree structure. As a result, on the actual layout, like the elements 13 and 16 at “c” and “z” as shown in FIG. 3, some of the elements may be connected to a clock supply circuit 19 through remote buffers 17 and 18, respectively, and therefore the wiring lengths of the elements may be disadvantageously larger than those of the other elements. Thus, this first method has disadvantages in that a phase difference is large, routing resources are greatly consumed, and high integration layout cannot be realized.
According to the second conventional method, placement is improved after forming a tree. At the initial placement, the scales of circuits to be inserted and the positions of placement and routing resources necessary for these circuits are not clearly given. Therefore, the second method has a disadvantage in that the layout of the circuits and the resources cannot sometimes be performed after the formation of the tree structure.